1. Field of the Invention
The present invention relates generally to the field of memory management and, more specifically, to multi-class data cache policies.
2. Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as “L2 cache”). The L2 cache is a large on-chip memory that serves as an intermediate point between an external memory (e.g., frame buffer memory) and internal clients of the memory subsystem (referred to herein as the “clients”). The L2 cache temporarily stores data being used by the various clients. This data may be retrieved from or written to an external memory (referred to herein as “DRAM”). The clients may re-use data that is stored in the L2 cache while performing certain operations.
During a read operation, a client may request data from the L2 cache that is not currently stored in the L2 cache and, therefore, has to be retrieved from the DRAM. A read operation where the data has to be retrieved from the DRAM is processed in significantly more clock cycles than a read operation where the data is retrieved directly from the L2 cache. Thus, overall system performance may be severely impacted if data has to be retrieved from the DRAM for a significant number of read operations. However, since the memory space allocated to the L2 cache is limited, the data resident in the L2 cache needs to be routinely evicted to free up memory space for future read or write operations transmitted by the clients. If data resident in the L2 cache is not evicted frequently enough, then future read and write operations have to be stalled until there is space in the L2 cache to process those operations. Again, such a dynamic can significantly impact overall system performance.
Conventional eviction schemes usually implement a policy where the least recently used data is evicted from the cache. However, in certain systems, where the use patterns of data vary, such an approach may not strike the appropriate balance between evicting data quickly to make room for future read and write operations and allowing data to remain in the cache long enough to be reused so that data requests to the external memory can be avoided.
As the foregoing illustrates, what is needed in the art is a more efficient mechanism for determining which data should be evicted first from an intermediate cache, such as an L2 cache.